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EURODAC
1994
IEEE

MOS VLSI circuit simulation by hardware accelerator using semi-natural models

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MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). The acceleration factor obtains of 3-4 order with respect to the Spice-2 program on VAX-11/780. The basic idea of the accelerator is to use real transistors instead of their mathematical models. In addition the accelerator concurrently uses 16processors and programmable communications between processors and distributed memory, the waveform relaxation method and Spice-like input language. for the multivariant circuit simulation, optimization, statistical analysis, and for the percent of parametrical defect determination. A radical solution to these problems would be to use a hardware accelerator. There are several commercial implementation of specific hardware accelerators for VLSI circuit simulation: the SPICE ACCELERATOR system by Weitek Corporation (has the acceleration factor 10-40 in comparison with Spice...
Victor V. Denisenko
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1994
Where EURODAC
Authors Victor V. Denisenko
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