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ICCAD
2002
IEEE
116views Hardware» more  ICCAD 2002»
14 years 1 months ago
Conflict driven techniques for improving deterministic test pattern generation
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xiji...
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
13 years 9 months ago
Deterministic Test Pattern Generation Techniques for Sequential Circuits
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
Ilker Hamzaoglu, Janak H. Patel
ET
2000
145views more  ET 2000»
13 years 4 months ago
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
Jaan Raik, Raimund Ubar
ETS
2009
IEEE
79views Hardware» more  ETS 2009»
13 years 2 months ago
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
Michael A. Kochte, Christian G. Zoellin, Hans-Joac...
ITC
2003
IEEE
134views Hardware» more  ITC 2003»
13 years 10 months ago
Effectiveness Improvement of ECR Tests
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
Wanli Jiang, Erik Peterson, Bob Robotka