8 search results - page 1 / 2 » Congestion Aware Layout Driven Logic Synthesis |
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
ICCAD
1991
IEEE
13 years 8 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
DAC
1994
ACM
13 years 8 months ago
1994
ACM
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...
INTEGRATION
2006
13 years 4 months ago
2006
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...