5 search results - page 1 / 1 » Construction of realistic gate sizing benchmarks with known ... |
ISPD
2012
ACM
12 years 4 days ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
GECCO
2005
Springer
13 years 10 months ago
2005
Springer
Several general purpose benchmark generators are now available in the literature. They are convenient tools in dynamic continuous optimization as they can produce test instances w...
ISPD
2003
ACM
13 years 9 months ago
2003
ACM
This paper studies the optimality, scalability and stability of stateof-the-art partitioning and placement algorithms. We present algorithms to construct two classes of benchmarks...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...