249 search results - page 2 / 50 » Context Sensitivity in Logical Modeling with Time Delays |
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Eventtransients (SET), is a ...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
CODES
2007
IEEE
13 years 9 months ago
2007
IEEE
The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at...