21 search results - page 2 / 5 » Control Techniques to Eliminate Voltage Emergencies in High ... |
PLDI
2003
ACM
13 years 10 months ago
2003
ACM
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
ASPLOS
1992
ACM
13 years 9 months ago
1992
ACM
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
SIGMETRICS
1999
ACM
13 years 9 months ago
1999
ACM
This paper examines NFS sensitivity to performance characteristics of emerging networks. We adopt an unusual method of inserting controlled delays into live systems to measure sen...