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» Cost-Efficient SHA Hardware Accelerators
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TVLSI
2008
123views more  TVLSI 2008»
13 years 4 months ago
Cost-Efficient SHA Hardware Accelerators
Abstract--This paper presents a new set of techniques for hardware implementations of Secure Hash Algorithm (SHA) hash functions. These techniques consist mostly in operation resch...
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Sta...
IADIS
2009
13 years 2 months ago
A strategy for cost efficient distributed data storage for in-memory OLAP
With the availability of inexpensive blade servers featuring 32 GB or more of main memory, memory-based engines such as the SAP NetWeaver Business Warehouse Accelerator are coming...
Olga Mordvinova, Oleksandr Shepil, Thomas Ludwig 0...
CODES
2005
IEEE
13 years 10 months ago
Future processors: flexible and modular
The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to...
Charlie Johnson, Jeff Welser
ARC
2010
Springer
183views Hardware» more  ARC 2010»
13 years 5 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
ISPASS
2005
IEEE
13 years 10 months ago
Anatomy and Performance of SSL Processing
A wide spectrum of e-commerce (B2B/B2C), banking, financial trading and other business applications require the exchange of data to be highly secure. The Secure Sockets Layer (SSL...
Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. ...