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» Crosstalk Reduction in Area Routing
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ASPDAC
2009
ACM
164views Hardware» more  ASPDAC 2009»
13 years 10 months ago
High-performance global routing with fast overflow reduction
Global routing is an important step for physical design. In this paper, we develop a new global router, NTUgr, that contains three major steps: prerouting, initial routing, and enh...
Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang
TVLSI
2002
78views more  TVLSI 2002»
13 years 5 months ago
Managing on-chip inductive effects
With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence o...
Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq ...
VLSID
2004
IEEE
85views VLSI» more  VLSID 2004»
14 years 6 months ago
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System
A key component of the Data-Intensive Architecture (DIVA) is the Processing-In-Memory (PIM) Routing Component (PiRC) that is responsible for efficient communication between PIM ch...
Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Drape...
FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
13 years 11 months ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
13 years 11 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra