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ASPLOS
2008
ACM
13 years 7 months ago
Tapping into the fountain of CPUs: on operating system support for programmable devices
The constant race for faster and more powerful CPUs is drawing to a close. No longer is it feasible to significantly increase the speed of the CPU without paying a crushing penalt...
Yaron Weinsberg, Danny Dolev, Tal Anker, Muli Ben-...
PPL
2008
185views more  PPL 2008»
13 years 5 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ARITH
2001
IEEE
13 years 9 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
ICMCS
2009
IEEE
102views Multimedia» more  ICMCS 2009»
13 years 3 months ago
Scalable HMM based inference engine in large vocabulary continuous speech recognition
Parallel scalability allows an application to efficiently utilize an increasing number of processing elements. In this paper we explore a design space for parallel scalability for...
Jike Chong, Kisun You, Youngmin Yi, Ekaterina Goni...
ANCS
2007
ACM
13 years 9 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos