Sciweavers

43 search results - page 3 / 9
» Cycle count accurate memory modeling in system level design
Sort
View
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
13 years 9 months ago
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems
This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze Vanill...
Tero Rissa, Adam Donlin, Wayne Luk
CODES
2009
IEEE
13 years 9 months ago
TotalProf: a fast and accurate retargetable source code profiler
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers...
3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
13 years 10 months ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...
SAMOS
2005
Springer
13 years 11 months ago
Micro-architecture Performance Estimation by Formula
An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design option...
Lucanus J. Simonson, Lei He
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
13 years 9 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer