5 search results - page 1 / 1 » Cycle time and slack optimization for VLSI-chips |
ICCAD
1999
IEEE
14 years 1 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
CODES
2008
IEEE
13 years 11 months ago
2008
IEEE
We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by su...
ASPDAC
2004
ACM
14 years 2 months ago
2004
ACM
- To minimize energy consumption by voltage scaling in design of heterogeneousreal-time embeddedsystems, it is necessary to perfom two distinct tasks: task scheduling (TS) and volt...
ICCAD
1994
IEEE
14 years 1 months ago
1994
IEEE
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
DAC
2008
ACM
13 years 11 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...