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DATE
2008
IEEE
168views Hardware» more  DATE 2008»
13 years 11 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
FDL
2007
IEEE
13 years 11 months ago
Modelling Alternatives for Cycle Approximate Bus TLMs
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...
Martin Radetzki, Rauf Salimi Khaligh
RTCSA
2007
IEEE
13 years 10 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
DAC
2004
ACM
14 years 5 months ago
Retargetable profiling for rapid, early system-level design space exploration
Fast and accurate estimation is critical for exploration of any dece in general. As we move to higher levels of abstraction, on of complete system designs at each level of abstrac...
Lukai Cai, Andreas Gerstlauer, Daniel Gajski
CODES
2005
IEEE
13 years 10 months ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan