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» DELTEST: Deterministic Test Generation for Gate-Delay Faults
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ETS
2006
IEEE
110views Hardware» more  ETS 2006»
13 years 11 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...
ICCAD
2002
IEEE
116views Hardware» more  ICCAD 2002»
14 years 2 months ago
Conflict driven techniques for improving deterministic test pattern generation
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xiji...
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
13 years 9 months ago
Deterministic Test Pattern Generation Techniques for Sequential Circuits
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
Ilker Hamzaoglu, Janak H. Patel
ATS
2009
IEEE
113views Hardware» more  ATS 2009»
14 years 14 hour ago
Deterministic Algorithms for ATPG under Leakage Constraints
—Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the re...
Gorschwin Fey
ISMVL
2005
IEEE
90views Hardware» more  ISMVL 2005»
13 years 10 months ago
Test Generation and Fault Localization for Quantum Circuits
It is believed that quantum computing will begin to have a practical impact in industry around year 2010. We propose an approach to test generation and fault localization for a wi...
Marek A. Perkowski, Jacob Biamonte, Martin Lukac