103 search results - page 2 / 21 » DPA Leakage Models for CMOS Logic Circuits |
CARDIS
2004
Springer
13 years 10 months ago
2004
Springer
CMOS gates consume different amounts of power whether their output has a falling or a rising edge. Therefore the overall power consumption of a CMOS circuit leaks information about...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a ...
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
CHES
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by “secure” random masking schemes, leak side-cha...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
Switching model captures the data-driven uncertainty in logic circuits in a comprehensive probabilistic framework. Switching is a critical factor that influences dynamic, active ...