6 search results - page 1 / 2 » DPA on Quasi Delay Insensitive Asynchronous Circuits: Formal... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a ...
CHES
2006
Springer
13 years 8 months ago
2006
Springer
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
FMSD
2000
13 years 4 months ago
2000
The study of asynchronous circuit behaviors in the presence of component and wire delays has received a great deal of attention. In this paper, we consider asynchronous circuits wh...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...