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» Datapath Scheduling using Dynamic Frequency Clocking
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ISVLSI
2002
IEEE
105views VLSI» more  ISVLSI 2002»
13 years 9 months ago
Datapath Scheduling using Dynamic Frequency Clocking
Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 5 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
ICCD
2003
IEEE
105views Hardware» more  ICCD 2003»
14 years 1 months ago
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling
— We model the power fluctuation as cycle-to-cycle power gradient and minimize the mean of the power gradients using ILP. We propose scheduling schemes for three modes of datapa...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
VLSID
2003
IEEE
134views VLSI» more  VLSID 2003»
14 years 5 months ago
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
Saraju P. Mohanty, N. Ranganathan