15 search results - page 1 / 3 » Decimal multiplier on FPGA using embedded binary multipliers |
FPL
2008
Springer
13 years 7 months ago
2008
Springer
FCCM
1998
IEEE
13 years 9 months ago
1998
IEEE
Abstract This paper presents a design for a reconfigurable multiplier array. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be emb...
ICCD
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— Decimal multiplication is important in many commercial applications including banking, tax calculation, currency conversion, and other financial areas. This paper pres...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
— We consider the problem of adding the partial products in the combinational decimal multiplier presented by Lang and Nannarelli. In the original paper this addition is done wit...
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...