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GLOBECOM
2007
IEEE
13 years 11 months ago
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders
Abstract—A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processin...
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon ...
GLOBECOM
2006
IEEE
13 years 11 months ago
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Ven...
CORR
2006
Springer
100views Education» more  CORR 2006»
13 years 5 months ago
Error Exponents of Low-Density Parity-Check Codes on the Binary Erasure Channel
-- We introduce a thermodynamic (large deviation) formalism for computing error exponents in error-correcting codes. Within this framework, we apply the heuristic cavity method fro...
Thierry Mora, Olivier Rivoire
ICC
2008
IEEE
141views Communications» more  ICC 2008»
13 years 12 months ago
Multilevel Structured Low-Density Parity-Check Codes
— Low-Density Parity-Check (LDPC) codes are typically characterized by a relatively high-complexity description, since a considerable amount of memory is required in order to sto...
Nicholas Bonello, Sheng Chen, Lajos Hanzo
ISCAS
2005
IEEE
136views Hardware» more  ISCAS 2005»
13 years 11 months ago
Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders
— Low-Density Parity-Check Convolutional Codes (LDPC-CCs) are an attractive alternative to their block-oriented counterparts, LDPC-BCs. In this paper, we introduce these codes an...
Ramkrishna Swamy, Stephen Bates, Tyler L. Brandon