36 search results - page 2 / 8 » Decoupled Interconnection of Distributed Memory Models |
CCGRID
2006
IEEE
13 years 11 months ago
2006
IEEE
A problem with running distributed shared memory applications in heterogeneous environments is that making optimal use of available resources often requires significant changes t...
CODES
2009
IEEE
13 years 11 months ago
2009
IEEE
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
SPDP
1991
IEEE
13 years 8 months ago
1991
IEEE
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
SCI
1999
Springer
13 years 9 months ago
1999
Springer
This paper describes the parallelization of a commercial molecular dynamics simulation code, GROMOS96, on a SCI (Scalable Coherent Interface) interconnected PC cluster. The underly...