38 search results - page 2 / 8 » Delay-Insensitive Ternary Logic |
FUIN
2007
13 years 5 months ago
2007
Abstract. Josephs and Udding’s DI-Algebra offers a convenient way of specifying and verifying designs that must rely upon delay-insensitive signalling between modules (asynchrono...
VLSID
1997
IEEE
13 years 9 months ago
1997
IEEE
Integer addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adde...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
DELTA
2006
IEEE
13 years 9 months ago
2006
IEEE
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
CHES
2006
Springer
13 years 9 months ago
2006
Springer
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...