Sciweavers

15 search results - page 2 / 3
» Desensitization for Power Reduction in Sequential Circuits
Sort
View
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
14 years 1 months ago
Simultaneous power and thermal integrity driven via stapling in 3D ICs
The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first ...
Hao Yu, Joanna Ho, Lei He
TC
2008
13 years 4 months ago
Low-Transition Test Pattern Generation for BIST-Based Applications
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
ICCAD
2010
IEEE
125views Hardware» more  ICCAD 2010»
13 years 2 months ago
Peak current reduction by simultaneous state replication and re-encoding
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...
Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou
DFT
1999
IEEE
131views VLSI» more  DFT 1999»
13 years 9 months ago
Optimal Vector Selection for Low Power BIST
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaud...
ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
14 years 1 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...