Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages

Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply voltage of some computational elements in the circuit, with the penalty of an increase of their execution delay. To reduce the dynamic power consumption, without degrading the performance determined assuming that the circuit operates at the highest available supply voltage, the supply voltage of computational elements off critical paths can be scaled down. Defined here as MinPdyn, the problem of minimizing the dynamic power consumption, under performance constraints, by scaling down the supply voltage of computational elements on non-critical paths is NP-hard in general. Solving MinPdyn for multi-phase clocked sequential circuits may allow to reduce their power consumption and the required number of registers. Reducing the number of registers also allows to reduce the power consumption, the number of control ...

• Type: Conference
• Year: 2001
• Where: ICCD
• Authors: Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria
• Keywords: Dynamic Power Consumption, Hardware, ICCD 2001, Possible Supply Voltage, Supply Voltage