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» Design Optimization for Robustness to Single Event Upsets
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IOLTS
2005
IEEE
163views Hardware» more  IOLTS 2005»
13 years 11 months ago
Modeling Soft-Error Susceptibility for IP Blocks
As device geometries continue to shrink, single event upsets are becoming of concern to a wider spectrum of system designers. These “soft errors” can be a nuisance or catastro...
Robert C. Aitken, Betina Hold
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
13 years 11 months ago
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Ca...
ICCD
2008
IEEE
121views Hardware» more  ICCD 2008»
14 years 2 months ago
Characterization and design of sequential circuit elements to combat soft error
- This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conve...
Hamed Abrishami, Safar Hatami, Massoud Pedram
DDECS
2007
IEEE
143views Hardware» more  DDECS 2007»
13 years 11 months ago
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques
Logic Soft Errors caused by radiation are a major concern when working with circuits that need to operate in harsh environments, such as space or avionics applications, where soft ...
Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Lu...
DATE
2009
IEEE
73views Hardware» more  DATE 2009»
14 years 1 days ago
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs
—Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are al...
Francesco Abate, Luca Sterpone, Massimo Violante, ...