98 search results - page 4 / 20 » Design Optimization for Robustness to Single Event Upsets |
ISQED
2008
IEEE
14 years 11 days ago
2008
IEEE
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
FPGA
2010
ACM
14 years 14 days ago
2010
ACM
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
IOLTS
2003
IEEE
13 years 11 months ago
2003
IEEE
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
APCSAC
2004
IEEE
13 years 9 months ago
2004
IEEE
As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurr...
MICRO
2006
IEEE
13 years 6 months ago
2006
IEEE
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...