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JISE
2011
55views more  JISE 2011»
12 years 12 months ago
Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits
Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu
CLEIEJ
2010
13 years 2 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...
DAC
2006
ACM
14 years 6 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....