153 search results - page 30 / 31 » Design Space Exploration in System Level Synthesis under Mem... |
SAMOS
2004
Springer
13 years 10 months ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
IPSN
2005
Springer
13 years 10 months ago
2005
Springer
Abstract— There is widespread agreement that a higher level programming model for sensor networks is needed. A variety of models have been developed, but the community is far fro...
NOCS
2007
IEEE
13 years 11 months ago
2007
IEEE
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Recently, under a fixed power budget, asymmetric multiprocessors (AMP) have been proposed to improve the performance of multi-threaded applications compared to symmetric multiproc...