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FDL
2006
IEEE
13 years 10 months ago
Design Structure Analysis and Transaction Recording in SystemC
We present an introspection/reflection framework for SystemC which extracts design-relevant structure information and transaction data under any LRM-2.1 compliant simulation kern...
Wolfgang Klingauf, Manuel Geffken
ACSD
2005
IEEE
121views Hardware» more  ACSD 2005»
13 years 10 months ago
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
We describe a toolbox for the analysis of Systems-on-achip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to bui...
Matthieu Moy, Florence Maraninchi, Laurent Maillet...
DATE
2008
IEEE
103views Hardware» more  DATE 2008»
13 years 11 months ago
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces
Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Simila...
Nicola Bombieri, Franco Fummi, Graziano Pravadelli
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
13 years 11 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
FDL
2006
IEEE
13 years 10 months ago
Formalizing TLM with Communicating State Machines
Transaction Level Models are widely being used as high-level reference models during embedded systems development. High simulation speed and great modeling flexibility are the ma...
Bernhard Niemann, Christian Haubelt