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ISVLSI
2007
IEEE

Code-coverage Based Test Vector Generation for SystemC Designs

10 years 9 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity increases, the validation effort reveal itself as a great barrier, consuming a considerable fraction of the total development time and resources. This work presents a methodology for automatic test vector generation for SystemC designs based on code coverage analysis that is complementary to the functional testing. Instead of create all vectors necessary to guarantee total coverage of the design, it uses code coverage information to generate test vectors to cover the portions of code not exercised by the Black-box Testing. Vectors are generated using a numerical optimization method which does not suffer from restrictions related to symbolic execution such as defining array reference values and loop boundaries. By using the methodology, we expect to guarantee total coverage of the DUV minimizing the fault of om...
Alair Dias Jr., Diógenes Cecilio da Silva J
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISVLSI
Authors Alair Dias Jr., Diógenes Cecilio da Silva Jr.
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