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2003
IEEE
123views Hardware» more  DATE 2003»
13 years 10 months ago
Parallel Processing Architectures for Reconfigurable Systems
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
Kees A. Vissers
ERSA
2009
91views Hardware» more  ERSA 2009»
13 years 2 months ago
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors
Configuration with Self-configured Data Path (CSDP) is a high speed configuration data loading method for Dynamically Reconfigurable Processors (DRPs). By using a prepared configu...
Toru Sano, Yoshiki Saito, Hideharu Amano
DAC
2000
ACM
13 years 9 months ago
System design of active basestations based on dynamically reconfigurable hardware
– This paper describes the system design and implementation of Active Basestations, a novel application of the run-time reconfigurable hardware technology whose applications have...
Athanassios Boulis, Mani B. Srivastava
DAC
2008
ACM
14 years 5 months ago
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to faulttolerant, Massively Parallel Multi-Processors Systems on Chip (MP...
Zhen Zhang, Alain Greiner, Sami Taktak
CF
2007
ACM
13 years 8 months ago
Reconfigurable hybrid interconnection for static and dynamic scientific applications
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
Shoaib Kamil, Ali Pinar, Daniel Gunter, Michael Li...