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» Design and Analysis of a Low Power VLIW DSP Core
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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 9 months ago
Security-Driven Exploration of Cryptography in DSP Cores
With the popularity of wireless communication devices a new important dimension of embedded systems design has arisen, that of security. This paper presents for the first time des...
Catherine H. Gebotys
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
13 years 9 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
13 years 9 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
13 years 10 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
FPL
2008
Springer
91views Hardware» more  FPL 2008»
13 years 6 months ago
Power efficient DSP datapath configuration methodology for FPGA
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
Stephen McKeown, Roger Woods, John McAllister