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TVLSI
2008
164views more  TVLSI 2008»
13 years 5 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
14 years 3 days ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu
VLDB
1999
ACM
131views Database» more  VLDB 1999»
13 years 10 months ago
High-Performance Extensible Indexing
Today’s object-relational DBMSs (ORDBMSs) are designed to support novel application domains by providing an extensible architecture, supplemented by domain-specific database ex...
Marcel Kornacker
SIGCOMM
2009
ACM
14 years 8 days ago
Energy-aware performance optimization for next-generation green network equipment
Besides a more widespread sensitivity to ecological issues, the interest in energy-efficient network technologies springs from heavy and critical economical needs, since both ener...
Raffaele Bolla, Roberto Bruschi, Franco Davoli, An...
JCM
2010
119views more  JCM 2010»
13 years 4 months ago
Evaluation of Router Implementations for Explicit Congestion Control Schemes
— Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require ...
Simon Hauger, Michael Scharf, Jochen Kögel, C...