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2008

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

8 years 5 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose FLEXBUS, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. FLEXBUS achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge bypass, and component re-mapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time re-configuration of FLEXBUS based architectures. The techniques underlying FLEX...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2008
Where TVLSI
Authors Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
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