Sciweavers

33 search results - page 5 / 7
» Design and Implementation of High-Performance Memory Systems...
Sort
View
MICRO
2010
IEEE
189views Hardware» more  MICRO 2010»
13 years 3 months ago
A Dynamically Adaptable Hardware Transactional Memory
Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
SIGGRAPH
2000
ACM
13 years 10 months ago
The WarpEngine: an architecture for the post-polygonal age
We present the WarpEngine, an architecture designed for realtime image-based rendering of natural scenes from arbitrary viewpoints. The modeling primitives are real-world images w...
Voicu Popescu, John G. Eyles, Anselmo Lastra, Josh...
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 6 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
TPDS
2010
260views more  TPDS 2010»
13 years 4 months ago
Real-Time Modeling of Wheel-Rail Contact Laws with System-On-Chip
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...
Yongji Zhou, T. X. Mei, Steven Freear
OOPSLA
2009
Springer
14 years 9 days ago
A concurrent dynamic analysis framework for multicore hardware
Software has spent the bounty of Moore’s law by solving harder problems and exploiting abstractions, such as highlevel languages, virtual machine technology, binary rewritdynami...
Jungwoo Ha, Matthew Arnold, Stephen M. Blackburn, ...