57 search results - page 4 / 12 » Design and Implementation of Multiple Addresses Parallel Tra... |
APPT
2009
Springer
13 years 9 months ago
2009
Springer
Abstract. In many-core CMP architectures, the cache coherence protocol is a key component since it can add requirements of area and power consumption to the final design and, there...
TMM
2002
13 years 5 months ago
2002
With the rapid performance improvements in low-cost PCs, it becomes increasingly practical and cost-effective to implement large-scale video-on-demand (VoD) systems around parallel...
FPL
2005
Springer
13 years 11 months ago
2005
Springer
String pattern matching is a computationally expensive task, and when implemented in hardware, it can consume a large amount of resources for processing and storage. This paper pr...
NOCS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
NETWORKING
2007
13 years 7 months ago
2007
Abstract. Parallel shared memory (PSM) routers represent an architectural approach for addressing the high memory bandwidth requirements dictated by output-queued switches. A funda...