243 search results - page 1 / 49 » Design and Implementation of a CFAR Processor for Target Det... |
FPL
2004
Springer
13 years 10 months ago
2004
Springer
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processor...
LSSC
2005
Springer
13 years 10 months ago
2005
Springer
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adap...
ACMSE
2011
ACM
12 years 5 months ago
2011
ACM
This paper describes the adaptation of a modern compiler construction course to target an FPGA-based hardware platform used throughout our computer science curriculum. One of the ...
ICIP
2009
IEEE
13 years 2 months ago
2009
IEEE
We introduce a new SIR particle filter that performs tracking in a joint feature space where pixel domain data are fused with measurements obtained from an 18-channel modulation d...
JSA
2010
12 years 11 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...