Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processor...
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adap...
Ivan Garvanov, Christo A. Kabakchiev, Plamen Daska...
This paper describes the adaptation of a modern compiler construction course to target an FPGA-based hardware platform used throughout our computer science curriculum. One of the ...
We introduce a new SIR particle filter that performs tracking in a joint feature space where pixel domain data are fused with measurements obtained from an 18-channel modulation d...
Colin M. Johnston, Nick A. Mould, Joseph P. Havlic...
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...