220 search results - page 4 / 44 » Design and analysis of optimal adaptive de-jitter buffers |
GRID
2004
Springer
13 years 11 months ago
2004
Springer
In this paper, we present a resource conscious dynamic scheduling strategy for handling large volume computationally intensive loads in a Grid system involving multiple sources an...
DAC
1998
ACM
13 years 10 months ago
1998
ACM
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
DAC
2006
ACM
14 years 7 hour ago
2006
ACM
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and cont...
RTCSA
2009
IEEE
14 years 23 days ago
2009
IEEE
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
GLOBECOM
2008
IEEE
14 years 15 days ago
2008
IEEE
— We present a crosslayer framework for optimizing the performance of wireless networks as measured by applications or upper layer protocols. The approach combines adaptive modul...