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» Design and implementation of JPEG encoder IP core
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ISCAS
2002
IEEE
111views Hardware» more  ISCAS 2002»
13 years 10 months ago
CASCADE - configurable and scalable DSP environment
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
Tay-Jyi Lin, Chein-Wei Jen
ISCAS
2002
IEEE
190views Hardware» more  ISCAS 2002»
13 years 10 months ago
A high performance JPEG2000 architecture
—JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of ...
Kishore Andra, Chaitali Chakrabarti, Tinku Acharya
FCCM
2004
IEEE
121views VLSI» more  FCCM 2004»
13 years 9 months ago
Validation of an Advanced Encryption Standard (AES) IP Core
This paper describes the package of test bench code required to verify the Algotronix' AES IP Core. Several authors (see the references in [3]) have published papers detailing...
Valeri F. Tomashau, Tom Kean
CODES
2007
IEEE
14 years 4 days ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha
CASES
2008
ACM
13 years 7 months ago
Active control and digital rights management of integrated circuit IP cores
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
Yousra Alkabani, Farinaz Koushanfar