Sciweavers

135 search results - page 3 / 27
» Design challenges at 65nm and beyond
Sort
View
DAC
2009
ACM
14 years 6 months ago
SRAM parametric failure analysis
With aggressive technology scaling, SRAM design has been seriously challenged by the difficulties in analyzing rare failure events. In this paper we propose to create statistical ...
Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileg...
ISQED
2008
IEEE
101views Hardware» more  ISQED 2008»
14 years 5 days ago
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations
Large-scale process fluctuations (particularly random device mismatches) at nanoscale technologies bring about highdimensional strongly nonlinear performance variations that canno...
Xin Li, Yu Cao
DAC
2006
ACM
14 years 6 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
ISLPED
2010
ACM
236views Hardware» more  ISLPED 2010»
13 years 6 months ago
Analysis and design of ultra low power thermoelectric energy harvesting systems
Thermal energy harvesting using micro-scale thermoelectric generators is a promising approach to alleviate the power supply challenge in ultra low power systems. In thermal energy...
Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaush...
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
14 years 18 days ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert