102 search results - page 2 / 21 » Design of Clock Distribution Networks in Presence of Process... |
DAC
2009
ACM
13 years 10 months ago
2009
ACM
We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modu...
INTEGRATION
2008
13 years 5 months ago
2008
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non...
ISPD
2006
ACM
13 years 11 months ago
2006
ACM
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
ISQED
2007
IEEE
14 years 1 days ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...