3 search results - page 1 / 1 » Design of FPGA interconnect for multilevel metalization |
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
In this paper, we propose a new multi-objective multilevel K-way partitioning which is aware of resource utilization distribution, assuming the resource utilization for a partitio...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
ASIC provides more than an order of magnitude advantage in terms of density, speed, and power requirement per gate. However, economic (cost of masks) and technological (deep micro...