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HPCA
2000
IEEE
11 years 4 months ago
Design of a Parallel Vector Access Unit for SDRAM Memory Systems
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...
SPAA
2000
ACM
11 years 4 months ago
Algorithmic foundations for a parallel vector access memory system
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with str...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...
ISCA
2003
IEEE
101views Hardware» more  ISCA 2003»
11 years 4 months ago
Overcoming the Limitations of Conventional Vector Processors
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
Christoforos E. Kozyrakis, David A. Patterson
DATE
2008
IEEE
133views Hardware» more  DATE 2008»
11 years 6 months ago
Memory Organization with Multi-Pattern Parallel Accesses
We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high ...
Arseni Vitkovski, Georgi Kuzmanov, Georgi Gaydadji...
CASES
2008
ACM
11 years 1 months ago
Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware
Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also n...
Hoseok Chang, Wonyong Sung
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