27 search results - page 1 / 6 » Design of a Parallel Vector Access Unit for SDRAM Memory Sys... |
HPCA
2000
IEEE
13 years 9 months ago
2000
IEEE
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
SPAA
2000
ACM
13 years 9 months ago
2000
ACM
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with str...
ISCA
2003
IEEE
13 years 10 months ago
2003
IEEE
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high ...
CASES
2008
ACM
13 years 7 months ago
2008
ACM
Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also n...