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» Design of a Reversible Binary Coded Decimal Adder by Using R...
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VLSID
2005
IEEE
124views VLSI» more  VLSID 2005»
13 years 11 months ago
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
ASAP
2007
IEEE
169views Hardware» more  ASAP 2007»
13 years 11 months ago
Reduced Delay BCD Adder
Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 ...
A. A. Bayrakci, A. Akkas
CORR
2010
Springer
196views Education» more  CORR 2010»
13 years 5 months ago
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computin...
H. G. Rangaraju, U. Venugopal, K. N. Muralidhara, ...