63 search results - page 13 / 13 » Designing High Bandwidth On-Chip Caches |
PDP
2010
IEEE
13 years 10 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
ICWS
2009
IEEE
14 years 2 months ago
2009
IEEE
The main memory management has been a critical issue to provide high performance in web cluster systems. To overcome the speed gap between processors and disks, many prefetch sche...
MICRO
2008
IEEE
14 years 5 days ago
2008
IEEE
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...