49 search results - page 1 / 10 » Designing logic circuits for probabilistic computation in th... |
DAC
2005
ACM
14 years 5 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on ...
IOLTS
2006
IEEE
13 years 10 months ago
2006
IEEE
So far, performance and reliability of circuits have been determined by worst-case characterization of silicon and environmental noise. As new deep sub-micron technologies exacerb...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Metallic Carbon Nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variat...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...