23 search results - page 1 / 5 » Designs for Reducing Test Time of Distributed Small Embedded... |
DFT
2004
IEEE
13 years 9 months ago
2004
IEEE
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper proposes a diagnosis scheme aimed at reducing diagnosis time of distributed small embedded SRAMs (e-SRAMs). This scheme improves the one proposed in [7, 8]. The improve...
ATS
2001
IEEE
13 years 9 months ago
2001
IEEE
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...