Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
Paul D. Gross, Ravishankar Arunachalam, Karthik Ra...
Crosstalk aggressor alignment induces significant interconnect delay variation and needs to be taken into account in a statistical timer. In this paper, we approximate crosstalk ...
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
Real-time schedulability theory requires a priori knowledge of the worst-case execution time (WCET) of every task in the system. Fundamental to the calculation of WCET is a schedu...
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...