30 search results - page 3 / 6 » Diagnosis of Hold Time Defects |
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experi...
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
Faster defect localization is achieved by combining IC simulations and internal measurements. Time resolved photon emission records photons emitted during commutations (current) r...
DATE
2007
IEEE
14 years 4 days ago
2007
IEEE
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
EOR
2008
13 years 5 months ago
2008
The problem of scheduling the production of new and recoverable defective items of the same product manufactured on the same facility is studied. Items are processed in batches. E...
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...