47 search results - page 2 / 10 » Digital Circuit Verification Using Partially-Ordered State M... |
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
FMICS
2008
Springer
13 years 7 months ago
2008
Springer
Different approaches have been developed to mitigate the state space explosion of model checking techniques. Among them, symbolic verification techniques use efficient representati...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
FMCAD
2007
Springer
13 years 9 months ago
2007
Springer
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates the verification of digital circuits us...