ISQED 2003 - PDF Preprint Papers

ISQED 2003 International Symposium on Quality Electronic Design

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ISQED
2003
IEEE

644views Hardware» more ISQED 2003»

Procedural Analog Design (PAD) Tool

13 years 10 months ago

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Danica Stefanovic, Maher Kayal, Marc Pastre, Vanco...

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Id	Views	Title	Status

1	644	Procedural Analog Design (PAD) Tool	claim
2	303	Design and Analysis of Low-Voltage Current-Mode Logic Buffers	claim
3	233	Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC	claim
4	215	Low-Cost and Real-Time Super-Resolution over a Video Encoder IP	claim
5	147	On Structural vs. Functional Testing for Delay Faults	claim
6	134	Concurrent Fault Detection in Random Combinational Logic	claim
7	133	Analyzing Internal-Switching Induced Simultaneous Switching Noise	claim
8	133	Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow	claim
9	127	Statistical Modeling for Circuit Simulation	claim
10	123	Advanced Module Packaging Method	claim
11	121	Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization	claim
12	119	System and Framework for QA of Process Design Kits	claim
13	116	Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics	claim
14	113	Using Integer Equations for High Level Formal Verification Property Checking	claim
15	109	Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers	claim
16	109	Modeling and Analysis of Power Distribution Networks for Gigabit Applications	claim
17	104	Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic	claim
18	104	A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design	claim
19	104	On-Chip Interconnect Inductance - Friend or Foe (Invited)	claim
20	104	Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis	claim
21	102	Modeling Crosstalk Induced Delay	claim
22	96	New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains	claim
23	96	Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint	claim
24	92	Parameterized Macrocells with Accurate Delay Models for Core-Based Designs	claim
25	87	Coupled Simulation of Circuit and Piezoelectric Laminates	claim
26	86	Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform	claim
27	85	Interoperability Beyond Design: Sharing Knowledge between Design and Manufacturing	claim
28	85	Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets	claim
29	85	PDL: A New Physical Synthesis Methodology	claim
30	83	Compact Dictionaries for Fault Diagnosis in BIST	claim
31	78	An Embedded IDDQ Testing Architecture and Technique	claim
32	75	Quantifying Error in Dynamic Power Estimation of CMOS Circuits	claim
33	73	A Novel Clocking Strategy for Dynamic Circuits	claim
34	73	Solving the SoC Test Scheduling Problem Using Network Flow and Reconfigurable Wrappers	claim
35	71	A Proposal for Routing-Based Timing-Driven Scan Chain Ordering	claim
36	71	Revisiting the Noise Figure Design Metric for Digital Communication Receiver	claim
37	60	Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains	claim

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